As technology advances, the importance of logic scaling continues to grow. However, traditional approaches to scaling of standard cells (e.g., the building blocks of logic design) are no longer effective due to lithographic limitations. In recent years, cross-coupling techniques have been implemented to mitigate the effects of such lithographic limitations to provide continued scaling of standard cells. Typical cross-coupling techniques, for instance, utilize metal layer structures to perform cross-coupling. For example, FIG. 1 schematically illustrates a cross-coupling-based multiplexer design using metal1 layer structures 101 and metal2 layer structures 103 to connect various gate structures 105, gate contacts 107, diffusion contacts 109, diffusion regions 111, and via structures 113 (e.g., via0, via1, etc.). As depicted, the cross-coupling of the multiplexer design requires three contacted poly pitches (3-CPP), causing the multiplexer design to stretch over nine gate grids (9-PC grids). Moreover, a 3-CPP-based flip-flop design (not shown for illustrative convenience) generally requires at least twenty-four gate grids (24-PC grids). To reduce cell size requirements, 2-CPP cross-coupling-based designs for multiplexers, flip-flops, and other standard cells may be implemented. However, typical 2-CPP cross-coupling-based design implementations (e.g., using trench silicide routing) are more costly, complex, and susceptible to leakage and damage to dielectric.
A need therefore exists for more effective and efficient 2-CPP cross-coupling-based designs that avoid significant increases in cost, complexity, or susceptibility to leakage and damage, and enabling methodology.